The present invention relates generally to integrated circuit devices and, more particularly, to low voltage transistor and logic devices with multiple, stacked piezoelectronic layers.
Field Effect Transistors (FETs) support the standard computer architecture (CMOS) currently used in logic and memory. Their shrinking size over several decades, following Moore's law, led to enormous increases in speed and reductions in voltage, as predicted by Dennard scaling theory. However, starting around 2003, supply voltages could no longer be reduced, and that meant clock speeds had to be limited to prevent excessive power densities. Discovery of a fast, low voltage switching device, based on a different principle of operation, has become critical for the continued pace of information technology.
One way in which the approach could be different would be to have the voltage that controls the switching device transduced into another energy state, such as pressure, which is gated and then transduced back into a voltage or current at the output. With mechanical amplification in the case of pressure transduction, it is possible to have a very small input voltage control a rather large output. The result is a switch for logic and memory that operates at an extremely low power density.
It is also desirable to find a technology that can build multi-layer structures that open up significant new applications, such as high capacity multilayer memories and combinations of logic and memory at different levels optimized to reduce wiring length. Such structures are very difficult to make in CMOS because of the need for all FETs to be formed in single crystal silicon. Technologies based on other materials may allow more three-dimensional structures.